Zoology: Measuring and Improving Recall in Efficient Language Models โ part 10/14
Cleaned-text code points [139148, 154481). Bibliography omitted here; source.md includes it.
Further, any ๐ i โ ( โฌโฌ โ ) {\bf E}_{i}\in\left(\cal{BB}^{*}\right) can be expressed as a product of 2 โ log โก e โ n โ d 2\log{end} butterfly factor matrices. Then by Lemma H.16 and Lemma H.11 we can compute ๐ i โ ๐ โฒ {\bf E}_{i}\bm{x^{\prime}} in by stacking 2 โ log โก e โ n โ d 2\log{end} ( n , d , L , e โ n , d ) โ BaseConv \left(n,d,L,en,d\right)-\text{{BaseConv}} models each with L = ๐ช โก ( 1 ) L=\mathcal{O}(1) . Because ๐ {\bf E} has width w w , Lemma H.11 implies that composing with each ๐ i {\bf E}_{i} for 1 โค i โค w 1\leq i\leq w constructs a final model with ๐ช โก ( w โ log โก ( e โ n โ d ) ) \mathcal{O}(w\log(end)) layers. โ
Finally, the kaleidoscope hierarchy is related to linear arithmetic circuits via the following result. We note that in [ Dao et al., 2020 ] it is assumed that w = s w=s , yet inspection of the proof yields the following stronger result:
###### Theorem H.19 ( [ Dao et al., 2020 ] ) .
Let ๐ {\bf M} be an n ร n n\times n matrix such that multiplication of ๐ {\bf M} times an arbitrary vector ๐ฎ \bm{u} can be be represented as ( n , s , ฮ , w ) (n,s,\Delta,w) -linear arithmetic circuit ๐ \mathcal{C} . Then, ๐ โ ( โฌโฌ โ ) ๐ช โก ( w / n ) ๐ช โก ( ฮ ) {\bf M}\in\left(\cal{BB}^{*}\right)^{\mathcal{O}(\Delta)}_{\mathcal{O}(w/n)} .
We combine Theorem H.19 and Lemma H.18 to show that BaseConv can compute any linear arithmetic circuit with polylogarithmic factors in ฮ \Delta .
###### Corollary H.20 .
For any ( n โ d , s , ฮ , w ) (nd,s,\Delta,w) -linear arithmetic circuit ๐ \mathcal{C} that can be represented by a matrix ๐ โ โ n โ d ร n โ d {\bf M}\in\mathbbm{R}^{nd\times nd} multiplied by a vector ๐ฑ โ โ n โ d \bm{x}\in\mathbbm{R}^{nd} , there exists an equivalent ( n , ฮ โฒ , d , w , d ) โ BaseConv \left(n,\Delta^{\prime},d,w,d\right)-\text{{BaseConv}} with ฮ โฒ = ๐ช โก ( ฮ โ log โก ( w ) ) \Delta^{\prime}=\mathcal{O}(\Delta\log(w)) such that ๐ โ ๐ฑ = BaseConv โ ( ๐ฎ , ๐ก ) {\bf M}\bm{x}=\textsc{BaseConv}\left({\bm{u},\bm{h}}\right) where ๐ฑ \bm{x} is the row major form of ๐ฎ โ โ n ร d \bm{u}\in\mathbbm{R}^{n\times d} .
### H.5 General Arithmetic Circuits
We are now ready to prove the result that yields the equivalency between arithmetic circuits and BaseConv .
###### Theorem H.21 .
For any ( n โ d , s , ฮ , w ) (nd,s,\Delta,w) -arithmetic circuit ๐ \mathcal{C} , there exists an equivalent ( N , ฮ โฒ , d , N โฒ , d โฒ ) โ BaseConv \left(N,\Delta^{\prime},d,N^{\prime},d^{\prime}\right)-\text{{BaseConv}} with N = n , ฮ โฒ = ๐ช โก ( ฮ โ log โก w ) N=n,\Delta^{\prime}=\mathcal{O}(\Delta\log{w}) , N โฒ = ๐ช โก ( w ) , d โฒ = d N^{\prime}=\mathcal{O}(w),d^{\prime}=d that simulates ๐ \mathcal{C} .
For the readerโs convenience, we begin with a proof sketch and then provide the details afterwards.
###### Proof Sketch of Theorem H.21 .
Let us layer ๐ \mathcal{C} so that each layer ๐ โ \mathcal{C}_{\ell} for โ โ [ L ๐ ] \ell\in[L_{\mathcal{C}}] either only has linear gates or multiplication gates, where the number of such layers L ๐ = ๐ช โก ( ฮ ) L_{\mathcal{C}}=\mathcal{O}(\Delta) . The composition of all ๐ โ \mathcal{C}_{\ell} layers results in ๐ \mathcal{C} . We use ๐ โ + 1 โ โ w \bm{z}^{\ell+1}\in\mathbbm{R}^{w} to denote the output of the โ \ell -th layer ๐ โ \mathcal{C}_{\ell} which feeds as the input to the ( โ + 1 ) (\ell+1) -th layer ๐ โ + 1 \mathcal{C}_{\ell+1} . Here, we note that if we can simulate each ๐ โ \mathcal{C}_{\ell} with BaseConv , then we can simulate the entire layered circuit ๐ \mathcal{C} due to Lemma H.11 .
Now, if the layer ๐ โ lin \mathcal{C}_{\ell}^{\mathrm{lin}} is a linear layer (with only addition gates), then it can be represented by a matrix ๐ด โ โ w ร w \bm{M}\in\mathbbm{R}^{w\times w} multiplied by ๐ โ โ โ w \bm{z}^{\ell}\in\mathbbm{R}^{w} (We can append with 0 0 s if necessary so that the input from the previous gates can be written as w w -length vector). Thus, we can apply Corollary H.20 to simulate ๐ โ lin \mathcal{C}_{\ell}^{\mathrm{lin}} with an equivalent ( n , log โก w , d , ๐ช โก ( log โก w ) , d ) โ BaseConv \left(n,\log{w},d,\mathcal{O}(\log{w}),d\right)-\text{{BaseConv}} model.
Next, if ๐ โ mult \mathcal{C}_{\ell}^{\mathrm{mult}} instead consists of only the multiplication gates. Then, we note here that the output ๐ โ \bm{z}^{\ell} may not exactly equal the input to ๐ โ mult \mathcal{C}_{\ell}^{\mathrm{mult}} . Nevertheless, we can apply a ๐ช โก ( w ) \mathcal{O}(w) sparse linear map ๐ โ โ w ร w {\bf R}\in\mathbbm{R}^{w\times w} so that ๐ โ ๐ โ {\bf R}\bm{z}^{\ell} yields vectors ๐ 1 , ๐ 2 , \bm{v}^{1},\bm{v}^{2}, and ๐ 3 \bm{v}^{3} , where ๐ 1 \bm{v}_{1} constitutes the โfirstโ input to all the multiplication gates and ๐ 2 \bm{v}_{2} constitutes all the โsecondโ inputs while ๐ 3 \bm{v}^{3} consists of all entries needed as inputs in the subsequent layers. That is, for the i i th gate in ๐ โ mult \mathcal{C}_{\ell}^{\mathrm{mult}} , we compute ๐ i 1 โ
๐ i 2 \bm{v}^{1}_{i}\cdot\bm{v}^{2}_{i} . This implies that for all the gates in ๐ โ mult \mathcal{C}_{\ell}^{\mathrm{mult}} , we can simply compute ๐ 1 โ ๐ 2 \bm{v}_{1}\odot\bm{v}_{2} . To this end, we use the ๐๐๐๐๐๐๐๐ {\tt remember} primitive with constant number of layers from Proposition H.10 to define a ( n , ๐ช โก ( log โก w ) , d , w , d ) โ BaseConv \left(n,\mathcal{O}(\log{w}),d,w,d\right)-\text{{BaseConv}} model that remembers ๐ 3 \bm{v}^{3} while performing the Hadamard product of ๐ 1 \bm{v}^{1} with ๐ 2 \bm{v}^{2} .
Overall, we can then collect all the resulting BaseConv layers and compose them as in Lemma H.11 to simulate ๐ \mathcal{C} . Overall, the number of layers used is given by ๐ช โก ( ฮ โ log โก w ) \mathcal{O}(\Delta\log{w}) while the internal dimension remains fixed at w w . โ
Using the outline in the proof sketch, we now delve into a detailed analysis of the arithmetic circuit ๐ \mathcal{C} to an equivalent BaseConv model.
###### Proof of Theorem H.21 .
Let ๐ โ โ n โ d \bm{u}\in\mathbbm{R}^{nd} be the input to the arithmetic circuit ๐ \mathcal{C} with depth ฮ \Delta and width w w . We begin by rearranging the circuit into layers of addition and multiplication gates. That is, each layer ๐ โ \mathcal{C}^{\ell} has either all addition gates or all multiplication gates. This allows us to readily apply the results from Section H.4 . Note here that we can assert that the number of such layers L ๐ = ๐ช โก ( ฮ ) L_{\mathcal{C}}=\mathcal{O}(\Delta) . Moreover, we construe the input to each such circuit as a vector of length w {w} by appending with extra 0s if necessary so that the composition of the layers results in a circuit equivalent to ๐ \mathcal{C} . See Fig. 8 for an example of such decomposition
Let ๐ โ โ โ w \bm{z}^{\ell}\in\mathbbm{R}^{w} denote the input to each layer ๐ โ \mathcal{C}_{\ell} for โ โ [ L ๐ ] \ell\in[L_{\mathcal{C}}] with ๐ 1 โก ( ๐ , ๐ w โ n โ d ) \bm{z}^{1}\equiv(\bm{u},\bm{0}^{w-nd}) . It is important to note here that we may not have ๐ โ + 1 โก ๐ โ โ ( ๐ โ ) \bm{z}^{\ell+1}\equiv\mathcal{C}_{\ell}(\bm{z}^{\ell}) since the inputs for gates at the ( โ + 1 ) (\ell+1) -th layer may come from any of the previous layers. We now handle the case of layers with addition gates, multiplication gates, and the intermediate stage separately.
##### Addition Gates.
Let ๐ โ lin \mathcal{C}_{\ell}^{\mathrm{lin}} denote an arbitrary linear layer which only contains the addition gates that takes in ๐ โ \bm{z}^{\ell} as input. We know that there exists a matrix ๐ โ โ w ร w โฒ {\bf M}\in\mathbbm{R}^{w\times w^{\prime}} such that we have ๐ โ lin โ ( ๐ โ ) โก ๐ โ ๐ โ . \mathcal{C}_{\ell}^{\mathrm{lin}}(\bm{z}^{\ell})\equiv{\bf M}\bm{z}^{\ell}. Here, note here that we may need entries from the vector ๐ โ \bm{z}^{\ell} in subsequent layers. Let s s be the total number of such entries, then for at each index for such entries i โ [ w ] i\in[w] , we have the corresponding index i s โ [ s ] i_{s}\in[s] . We then append the i i th standard row vector into the matrix ๐ {\bf M} to get the matrix ๐ โฒ โ โ w ร ( w โฒ + s ) {\bf M}^{\prime}\in\mathbbm{R}^{w\times(w^{\prime}+s)} so that we have ( ๐ โฒ โ ๐ โ ) โ [ j ] = { ( ๐ โ ๐ โ ) โ [ j ] if โ j < w โฒ ๐ โ โ [ i ] if โ j = w โฒ + i s \left({\bf M}^{\prime}\bm{z}^{\ell}\right)[j]=\begin{cases}\left({\bf M}\bm{z}^{\ell}\right)[j]&\text{if }j<w^{\prime}\\ \bm{z}^{\ell}[i]&\text{if }j=w^{\prime}+i_{s}\end{cases} Here, note that we must have w โฒ + s โค w w^{\prime}+s\leq w as w w is the width of the circuit. If needed, we then append the matrix ๐ โฒ {\bf M}^{\prime} with all-zero rows ๐ w \bm{0}^{w} so that we get the matrix ๐ โฒโฒ โ โ w ร w {\bf M}^{\prime\prime}\in\mathbbm{R}^{w\times w} . Note here that we have thus preserved all entries needed in subsequent layers and incorporated the output of the โ \ell th layer with the output ๐ โฒโฒ โ ๐ โ โก ๐ โ + 1 {\bf M}^{\prime\prime}\bm{z}^{\ell}\equiv\bm{z}^{\ell+1} serving as the input of the ( โ + 1 ) (\ell+1) -th layer. Applying Corollary H.20 then yields an equivalent ( n , ๐ช โก ( log โก w ) , d , w , d ) โ BaseConv \left(n,\mathcal{O}(\log{w}),d,w,d\right)-\text{{BaseConv}} model.
##### Multiplication Gates.
Next, we deal with the layer ๐ mult โ \mathcal{C}^{\ell}_{\mathrm{mult}} of multiplication gates by collecting the two inputs to each multiplication gates as ๐ 1 โ , ๐ 2 โ \bm{v}_{1}^{\ell},\bm{v}_{2}^{\ell} . Note that for the input ๐ โ โ โ w \bm{z}^{\ell}\in\mathbbm{R}^{w} from the previous layer, we will again have entries that need to be used in the subsequent layers that we will denote as ๐ 3 โ \bm{v}_{3}^{\ell} . We thus need to permute the entries of ๐ โ \bm{z}^{\ell} to get the vector [ ๐ 1 โ : : ๐ 2 โ : : ๐ 3 โ ] [\bm{v}_{1}^{\ell}::\bm{v}_{2}^{\ell}::\bm{v}_{3}^{\ell}] so that we can remember ๐ 3 โ \bm{v}_{3}^{\ell} while taking the Hadamard product ๐ 1 โ โ ๐ 2 โ \bm{v}_{1}^{\ell}\odot\bm{v}_{2}^{\ell} . To this end, we can achieve this permutation of entries using a ๐ช โก ( w ) \mathcal{O}(w) -sparse linear matrix 12 12 12 Each row of ๐ โ {\bf R}^{\ell} has exactly one non-zero entry. ๐ โ โ โ w ร w {\bf R}^{\ell}\in\mathbbm{R}^{w\times w} with which is equivalently represented by an ( w , w , 1 , w ) (w,w,1,w) -linear arithmetic circuit that simply moves the appropriate wires from the previous layer. This can again be achieved by a equivalent ( n , ๐ช โก ( log โก w ) , d , w , d ) โ BaseConv \left(n,\mathcal{O}(\log{w}),d,w,d\right)-\text{{BaseConv}} model. That is, ๐ โ โ ๐ โ {\bf R}^{\ell}\bm{z}^{\ell} has the following form: ๐ โ โ ๐ โ โก ( ๐ 1 โ ๐ 2 โ ๐ 3 โ ) . {\bf R}^{\ell}\bm{z}^{\ell}\equiv\begin{pmatrix}\bm{v}_{1}^{\ell}\\ \hline\cr\\ \bm{v}_{2}^{\ell}\\ \hline\cr\\ \bm{v}_{3}^{\ell}\end{pmatrix}. Next, we can now define a ( n , 1 , d , n , d ) โ BaseConv \left(n,1,d,n,d\right)-\text{{BaseConv}} which extracts ๐ 1 โ \bm{v}_{1}^{\ell} as the projection with the input to the remember primitive given by ๐ โ โก ( ๐ 2 โ , ๐ 3 โ , ๐ ) \bm{y}^{\ell}\equiv(\bm{v}_{2}^{\ell},\bm{v}_{3}^{\ell},\bm{0}) . We then specify the remember primitive as ๐๐๐๐๐๐๐๐ ( ๐ โ : ๐ 2 โ , ๐ 3 โ , ๐ 0 , ๐ 1 โ ) {\tt remember}\left(\bm{y}^{\ell}:\bm{v}_{2}^{\ell},\bm{v}_{3}^{\ell},\bm{e}_{0},\bm{v}_{1}^{\ell}\right) which computes the following ๐ โ + 1 \displaystyle\bm{z}^{\ell+1} โก ( ๐ 1 โ โ ( ๐ 0 โ ๐ 2 โ ) ๐ 3 โ ๐ ) \displaystyle\equiv\begin{pmatrix}\bm{v}_{1}^{\ell}\odot(\bm{e}_{0}\ast\bm{v}_{2}^{\ell})\\ \hline\cr\\ \bm{v}_{3}^{\ell}\\ \hline\cr\\ \bm{0}\end{pmatrix} โก ( ๐ 1 โ โ ๐ 2 โ ๐ 3 โ ๐ ) \displaystyle\equiv\begin{pmatrix}\bm{v}_{1}^{\ell}\odot\bm{v}_{2}^{\ell}\\ \hline\cr\\ \bm{v}_{3}^{\ell}\\ \hline\cr\\ \bm{0}\end{pmatrix} โก ๐ mult โ โ ( ๐ โ ) โ โ w . \displaystyle\equiv\mathcal{C}^{\ell}_{\mathrm{mult}}(\bm{z}^{\ell})\in\mathbbm{R}^{w}. Using Proposition H.10 , we know that this requires a ( n , ๐ช โก ( log โก w ) , d , w , d ) โ BaseConv \left(n,\mathcal{O}(\log{w}),d,w,d\right)-\text{{BaseConv}} which remembers the entries that will serve as inputs in subsequent layers while performing the Hadamard product ๐ 1 โ ๐ 2 \bm{v}^{1}\odot\bm{v}^{2} .
Overall, we can now stack all the resulting BaseConv layers and compose them as in Lemma H.11 to simulate ๐ \mathcal{C} . Overall, the number of layers blows up by ๐ช โก ( ฮ โ log โก w ) \mathcal{O}(\Delta\log{w}) while the internal dimension remains fixed at w w . โ
### H.6 The Retnet Reduction and Space Complexity for AR
We are now in a position to show that there exists an equivalent BaseConv model that can simulate a Retnet layer from Algorithm 6 . Recall that for an input sequence ๐ โ โ N ร d \bm{u}\in\mathbbm{R}^{N\times d} , we project the input using weight matrices ๐ A , ๐ C , ๐ V โ โ d ร d {\bf W}_{A},{\bf W}_{C},{\bf W}_{V}\in\mathbbm{R}^{d\times d} to ๐ , ๐ , ๐ โ โ N ร d {\bf A},{\bf C},{\bf V}\in\mathbbm{R}^{N\times d} and compute the following recurrence (see line 6 in Algorithm 6 ): ๐ n โก ฮณ ๐ n โ 1 + ( ๐ [ n , : ] ) โค ๐ [ n , : ] , \bm{z}^{n}\equiv\gamma\bm{z}^{n-1}+\left({\bf A}[n,:]\right)^{\top}{\bf V}[n,:], (6) where ๐ n โ โ d ร d \bm{z}^{n}\in\mathbbm{R}^{d\times d} . We unroll this recurrence to express each state ๐ n \bm{z}^{n} in terms of ๐ \bm{u} with coefficients given by ฮณ \gamma and the weight matrices ๐ A , ๐ C , ๐ V {\bf W}_{A},{\bf W}_{C},{\bf W}_{V} as follows: ๐ 0 \displaystyle\bm{z}^{0} โก ( ( ๐ ๐ A ) [ 0 , : ] ) โค ( ๐ ๐ V ) [ 0 , : ] \displaystyle\equiv\left(\left(\bm{u}{\bf W}_{A}\right)[0,:]\right)^{\top}\left(\bm{u}{\bf W}_{V}\right)[0,:] โก ( ๐ [ 0 , : ] ๐ A ) โค ( ๐ [ 0 , : ] ) ๐ V \displaystyle\equiv\left(\bm{u}[0,:]{\bf W}_{A}\right)^{\top}\left(\bm{u}[0,:]\right){\bf W}_{V} โก ๐ A โค ( ๐ [ 0 , : ] ) โค ( ๐ [ 0 , : ] ) ๐ V \displaystyle\equiv{\bf W}_{A}^{\top}\left(\bm{u}[0,:]\right)^{\top}\left(\bm{u}[0,:]\right){\bf W}_{V} โก ๐ A โค ( ๐ โค [ : , 0 ] ๐ [ 0 , : ] ) ๐ V . \displaystyle\equiv{\bf W}_{A}^{\top}\left(\bm{u}^{\top}[:,0]\bm{u}[0,:]\right){\bf W}_{V}. Similarly, we have ๐ 1 \displaystyle\bm{z}^{1} โก ฮณ ๐ 0 + ๐ A โค ( ๐ โค [ : , 1 ] ๐ [ 1 , : ] ) ๐ V \displaystyle\equiv\gamma\bm{z}^{0}+{\bf W}_{A}^{\top}\left(\bm{u}^{\top}[:,1]\bm{u}[1,:]\right){\bf W}_{V} โก ฮณ ( ๐ A โค ( ๐ โค [ : , 1 ] ๐ [ 0 , : ] ) ๐ V ) + ๐ A โค ( ๐ โค [ : , 1 ] ๐ [ 1 , : ] ) ๐ V \displaystyle\equiv\gamma\left({\bf W}_{A}^{\top}\left(\bm{u}^{\top}[:,1]\bm{u}[0,:]\right){\bf W}_{V}\right)+{\bf W}_{A}^{\top}\left(\bm{u}^{\top}[:,1]\bm{u}[1,:]\right){\bf W}_{V} โก ๐ A โค ( ฮณ ( ๐ โค [ : , 0 ] ๐ [ 0 , : ] ) + ๐ โค [ : , 1 ] ๐ [ 1 , : ] ) ๐ V \displaystyle\equiv{\bf W}_{A}^{\top}\left(\gamma\left(\bm{u}^{\top}[:,0]\bm{u}[0,:]\right)+\bm{u}^{\top}[:,1]\bm{u}[1,:]\right){\bf W}_{V} We can then generalize this to n โ [ N ] n\in[N] to get ๐ n โก ๐ A โค ( โ i = 0 n ฮณ n โ i ๐ โค [ : , i ] ๐ [ i , : ] ) ๐ V . \bm{z}^{n}\equiv{\bf W}_{A}^{\top}\left(\sum_{i=0}^{n}\gamma^{n-i}\bm{u}^{\top}[:,i]\bm{u}[i,:]\right){\bf W}_{V}. (7) The above helps us infer that ๐ n \bm{z}^{n} can be expressed as a polynomial in { ๐ โก [ 0 , 0 ] , ๐ โก [ 0 , 1 ] , โฆ , ๐ โก [ N โ 1 , d โ 1 ] } \{\bm{u}[0,0],\bm{u}[0,1],\ldots,\bm{u}[N-1,d-1]\} . For each polynomial, there exists an arithmetic circuit that computes the polynomial in a natural way, whence we can apply Theorem H.21 to get an equivalent BaseConv model.
###### Corollary H.22 .
For a RetNet model with ๐ช โก ( d 2 ) \mathcal{O}(d^{2}) parameters and N N layers, there exists an equivalent BaseConv model that uses ๐ช โก ( N โ d ) \mathcal{O}(Nd) parameters and ๐ช โก ( N โ log โก d ) \mathcal{O}(N\log{d}) layers.
###### Proof.